Synthesis-DFT Stitch CAD Engineer
Core
Develop and support Synthesis and DFT Stitch flows, methodologies, and tools for Snapdragon SoCs to optimize PPA (Power, Performance, Area) and shorten design cycle times.
Role type
Senior IC VLSI CAD Engineer (Synthesis/DFT Stitch)
Builds
Implementation tools and methodologies for mobile, compute, AI, and IoT chips
Domain
Semiconductor / VLSI / EDA
Required skills
VLSI CAD, Synthesis, DFT Stitch, Place and Route, EDA tool development, scripting (Python, TCL), regression test management, multi-voltage crossing analysis
Preferred skills
GenAI/ML for automation, patent-level innovation in area/power reduction, EDA vendor roadmap leadership
Technologies
Synopsys, Cadence, Python, TCL, Snapdragon SoC
Responsibilities
Develop DFT stitch flow leveraging Synopsys and Cadence; Improve SoC Synthesis and DFT Stitch methodologies; Enable new features from EDA tools; Develop methods for multi-voltage crossings; Support design teams via ticket queues; Interface with EDA vendors; Maintain regression testcases; Innovate on area/power reduction techniques.
Seniority
Senior, hands-on IC
