Package Design Engineer - Staff
Core
Design and optimize high-performance, energy-efficient server package structures and configurations for data center applications.
Role type
Staff IC Package Design Engineer
Builds
Physical designs of packages and modules for SoC, including new generation product package structures.
Domain
Semiconductor industry, IC packaging, data center hardware
Required skills
Cadence APD & SiP, Siemens Xpedition Package Designer (xPD), Constraint Manager, DRC/DFM/ERC, signal-integrity for high-speed IO, chip-package and package-board interaction knowledge
Preferred skills
Master's degree in EE/ME/Materials Science, 5+ years experience, Flip chip BGA/2.5D/3D Interposer knowledge, Cadence Allegro platform tools, SI/PI tools (XtractIM, PowerSI, HFSS, Q3D), substrate manufacturing process knowledge, high-speed interfaces (DDR, PCIe, UCIE), Calibre tool, RLGC model understanding
Technologies
Cadence APD, Siemens Xpedition, Cadence Allegro, XtractIM, PowerSI, HFSS, Q3D, Calibre
Responsibilities
Own and drive advanced package selection and configuration optimization; Perform package/SiP physical design, layout, optimization, DV, and tape out; Interface with multi-functional groups for feasibility analysis and design; Define design verification and automation strategy; Optimize package pin out and SI/PI requirements; Drive methodology innovations and efficiency improvements; Partner with BU PD team to optimize floorplan and bump placement.
Seniority
Staff, hands-on IC
