IC Package Layout Engineer, Staff
Core
Own and drive advanced package selection, new generation product package structure, and configuration optimization for SoC chips.
Role type
Staff IC Package Layout Engineer
Builds
Physical design of packages and modules for System-on-Chip (SoC) products.
Domain
Semiconductor packaging and System-in-Package (SiP) design.
Required skills
Package/SiP physical design and layout, Design Verification (DV), tape out, high-speed IO interfaces, electromagnetic field knowledge, chip-package and package-board interaction, SI/PI requirements, CAD tool development, floorplan optimization, bump placement.
Preferred skills
Electrical/material/thermal/mechanical engineering fundamentals, sophisticated package configurations (Flip chip BGA, 2.5D/3D Interposer), Cadence Allegro platform tools, SI/PI tools (XtractIM, PowerSI, HFSS, Q3D), substrate manufacturing process knowledge, high-speed interface understanding (DDR, PCIe, UCIE), Calibre tool usage, Design Rules Check (DRC) and Design for Manufacturing (DFM).
Technologies
Cadence APD, SiP, Allegro, XtractIM, PowerSI, HFSS, Q3D, Calibre, DDR, PCIe, UCIE.
Responsibilities
Define and develop design verification and automation strategy, interface with multi-functional groups for feasibility analysis, optimize package pin out, partner with Product Development (PD) team to optimize chip floorplan and bump placement, explore and evaluate new CAD tools and design flows.
Seniority
Staff, hands-on IC with strategic influence.
