ASIC DV Engineer, Principal/Mgr
Core
Define verification architecture and drive technical strategy for next-generation Ethernet switch ASICs, enabling scalable, high-performance networking solutions.
Role type
Principal ASIC Design Verification Manager
Builds
Ethernet switch ASICs (merchant silicon/switching ASIC)
Domain
Networking hardware / ASIC design
Required skills
System Verilog, UVM, SVA, Coverage-driven methodology, Emulation, FPGA validation, Ethernet switch architecture, Forwarding pipelines (L2/L3, ACLs, tunneling), Traffic management (QoS, scheduling, shaping), High-performance packet processing, System-level debugging, Cross-functional leadership
Preferred skills
Merchant silicon or switching ASIC experience (Broadcom/Marvell/Realtek/MTK), Mentorship of senior technical leaders
Technologies
System Verilog, UVM, SVA, FPGA
Responsibilities
Drive architecture definition and technical strategy for next-generation Ethernet switch ASICs; Define verification architecture from Module to System level; Drive cross-functional alignment with HW, SW, and Product teams; Ensure on-schedule execution with Arch and Design Team; Mentor senior technical leaders and influence organization-wide engineering direction
Seniority
Principal, strategy & mentorship
