Implementation Timing / STA Design Engineer
Core
Develop timing constraints, perform power analysis, and achieve timing closure for premium-tier SoCs in sub-3nm nodes.
Role type
Senior IC physical design engineer (timing)
Builds
Snapdragon SoCs for mobile, AI, and automotive sectors
Domain
Semiconductor / ASIC Design
Required skills
Static timing analysis (STA), power-aware synthesis, clock domain crossing (CDC), HM/SoC correlation, path pessimism analysis, corner analysis
Preferred skills
Scripting (Tcl, Perl, Python), RTL design collaboration, physical design collaboration
Technologies
Primetime, Fishtail/TCM
Responsibilities
Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis; Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks; Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores; Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing; Analyze timing across modes and corners, understand concepts like path pessimism and margins.
