Mask Layout Designer
Core
Develops block, macro, or chip level layouts and floorplans; leads teams to define and build macro level layouts based on design schematics and project requirements.
Role type
Senior IC mask layout designer (team lead)
Builds
Macro level layouts and floorplans for analog, mixed signal, RF, or digital chips
Domain
Semiconductor manufacturing / IC design
Required skills
Layout design and verification tools (Cadence, LVS, rmap), design rule manuals, electronic principles (currents, resistance, parasitic), PPA and yield optimization, troubleshooting and debugging, project management, team leadership
Preferred skills
Master's degree in Electrical/Electronic Engineering, experience with FINFET/CMOS/GATE ARRAY technologies, technical leadership experience, interaction with senior leadership, budget management
Technologies
Cadence, LVS, rmap
Responsibilities
Leads team to interpret schematics and develop complex macro level layouts; develops and communicates design guidelines and checklists; manages testing and validation of top-level designs; troubleshoots and debugs complex technical issues; re-scopes projects and reassigns resources; collaborates with internal teams and external stakeholders (Foundry, SoC)
Seniority
Senior, hands-on IC with team leadership
