CPU DFT Engineer
Core
Design and verify DFT and DFD architecture, implementation, and test plans for mixed signal and digital VLSI designs to ensure testability and debuggability.
Role type
Senior IC DFT Engineer (CPU/VLSI)
Builds
Testable and debuggable SoC designs for mobile and wireless chips
Domain
Semiconductor / VLSI / CPU Design
Required skills
Digital ASIC design, Verilog/VHDL, ASIC test, DFT, debug, Mentor Tessent tools, SOC level verification, TCL/Perl/Python/Shell scripting
Preferred skills
Commercial test generation tools, JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST, LBIST, test compression software
Technologies
Verilog, VHDL, Mentor Tessent, TCL, Perl, Python, Shell
Responsibilities
Create test vectors or oversee their creation, Validate DFT requirements are being met, Work with designers to increase test coverage, debug observability and flexibility, Verify post-PD designs meet DFT requirements, Work with test personnel to run tests
Seniority
Senior, hands-on IC
