DRAM PHY Designer, up to Staff
Core
Architect, design, and implement high-speed PHY circuits for memory-centric compute systems connecting compute and memory buses in data center, mobile, and XR applications.
Role type
Senior IC analog/RF engineer (memory PHY)
Builds
High-performance, low-power memory interfaces (LPDDR, HBM) and SoC blocks
Domain
Semiconductor, Memory Systems, High-Speed Interfaces
Required skills
High-speed PHY design, Analog building blocks, SERDES, Timing circuits (DLL/PLL), Signal integrity analysis, Power delivery optimization, Layout and floorplanning, Mixed-mode simulation
Preferred skills
Package design, Scripting (Perl/Python), DRAM datasheet expertise, EDA tool proficiency
Technologies
Virtuoso, RTL to GDS Flow, S-parameter models
Responsibilities
Architect and design high-speed PHY circuits; Create layouts optimizing placement, routing, and power; Simulate signal integrity and SNR with package/board models; Develop behavioral, timing, and power models for architecture choices; Floorplan circuits under manufacturing constraints; Collaborate with process, AI, and memory controller teams.
Seniority
Senior, hands-on IC with mentorship
