Wireless R&D IP Verification Sr Lead/Sr Engineer/Engineer
Core
Lead end-to-end verification for flagship Wireless IP (WAN, WLAN, GNSS, Bluetooth) using SystemVerilog/UVM.
Role type
Senior IC Digital Verification Engineer (Wireless IP)
Builds
Wireless IP cores for next-generation connected devices
Domain
Semiconductor / Wireless Communications
Required skills
SystemVerilog, UVM, Constraint-Random Verification, Coverage Closure, RTL Debugging, Formal Verification, Gate-Level Simulation (GLS), Python/Perl Scripting
Preferred skills
Wireless IP exposure (Wi-Fi, Modem PHY, DSP), Power-aware verification
Technologies
SystemVerilog, UVM, Verdi, Python, Perl
Responsibilities
Design analysis and verification planning, Develop test benches and write test cases, Write assertions and run simulations, Debug RTL and testbench issues, Maintain verification environments for scalability
Seniority
Senior, hands-on IC
