Staff Engineer, Analog Layout
Core
Drive physical implementation of key analog subsystems (PMUs, clocking, data converters) translating circuit architecture into silicon-ready layout meeting performance, area, matching, and reliability targets.
Role type
Staff Analog Layout Engineer
Builds
Custom analog layouts for leading-edge semiconductor chips (22nm, 12nm, beyond)
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: Corrected to 'physical work' or 'silicon chips' based on context, but strictly following the allowed list 'physical/clinical work' is the closest fit for hardware manufacturing, however, the prompt says 'physical/clinical work'. Let's re-evaluate the allowed list: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. The role builds physical chips. 'physical/clinical work' is the only option involving physical objects. I will use 'physical work' if allowed, but the list is fixed. I will map 'silicon-ready layout' to 'product features' or 'infrastructure'? No, it's hardware. The list is restrictive. Let's look at the instruction: 'one of: ...'. I must choose one. 'product features' is software. 'infrastructure' is usually cloud/ops. 'physical/clinical work' is the only one fitting hardware manufacturing. I will use 'physical/clinical work' as the closest semantic match for physical chip manufacturing, or perhaps 'product features' if interpreted as the physical product. Actually, 'infrastructure' could fit the 'silicon' aspect. But 'physical/clinical' is best for 'physical implementation'. I will select 'physical/clinical work' as the category for physical hardware creation.
Required skills
Analog IC layout, floorplanning, transistor-level layout, critical matching, shielding, parasitic extraction, LVS/DRC closure, tape-out, validation, production test support
Preferred skills
Experience with 22nm and 12nm technologies, circuit design review participation, manufacturing test plan development
Technologies
22nm, 12nm, PMUs, clocking, data converters
Responsibilities
Partner with analog designers on chip-level and block-level floorplanning and layout strategy; Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs; Execute transistor-level analog IC layout including critical matching, shielding, and parasitic-sensitive structures; Lead layout for complex blocks and supervise or review layout work from other layout engineers; Conduct layout design reviews and resolve action items; Attend circuit design reviews to provide layout feasibility input; Own parasitic extraction, LVS, DRC, antenna, and fill closure; Support prototype chip bring-up and testing; Support development of manufacturing test plans; Support Product Engineering and Applications Engineering on layout-related issues
Seniority
Staff, hands-on IC with mentorship responsibilities