MTS - DPG Layout
Core
Senior layout engineer responsible for full chip layout design, verification, and team leadership in advanced CMOS memory and semiconductor technologies.
Role type
Senior IC layout engineer (memory/semiconductor)
Builds
Full chip layouts for DRAM, SRAM, CAM, OTP, and analog blocks (PLL, ADC, DAC, LDO, etc.)
Domain
Semiconductor / VLSI / Memory
Required skills
Analog/custom layout design, Cadence VLE/VXL, Calibre DRC/LVS, DRAM/SRAM/CAM/OTP handling, Analog layout fundamentals (matching, EM/IR, latch-up), Physical layout verification, Project management, Scripting and automation, Team leadership
Preferred skills
AI tool usage for design/verification prompts, Technical publications
Technologies
Cadence VLE, Cadence VXL, Calibre
Responsibilities
Drive design and development of full chip layout; Perform layout verification (LVS/DRC/Antenna); Establish layout standards and methodologies; Guide junior team members; Collaborate with cross-functional teams (Design, Verification, CAD, DTCO); Manage project schedules and tape-outs; Validate AI outputs for design decisions.
Seniority
Senior, hands-on IC with team leadership
