Principal Design Engineer
Core
Design and verify major IO/datapath blocks (receivers, serializer, clock distribution, equalizers, ZQ calibration, ONFI training, wave pipelines) for high-speed memory and storage solutions, leveraging AI tools to accelerate exploration, sizing, and verification.
Role type
Principal IC Design Engineer (High-Speed IO)
Builds
High-performance memory and storage chips (DRAM interfaces, DDR4/5, LPDDR5/6, HBM3/4)
Domain
Semiconductor / High-Speed Digital IC Design
Deliverable
production ML models
Required skills
High-speed IO design, Physical design flows, Layout optimization, Parasitic extraction, CMOS device physics, BSIM modeling, AI tool usage (LLMs, agentic workflows), Prompt engineering
Preferred skills
DRAM interface experience, Custom AI agent deployment, RAG, Fine-tuning, Quantified productivity impact of AI changes
Technologies
LLMs, Code/RTL generation, Spec parsing, Waveform interpretation, Layout engines, DDR4/5, LPDDR5/6, HBM3/4, ONFI, BSIM
Responsibilities
Design and verify major IO/datapath blocks to meet performance specs, Champion AI adoption by evaluating tools and publishing methodologies, Work with integration and Apps teams to define interfaces, Document AI-augmented methodologies and mentor engineers
Seniority
Principal, hands-on IC design with mentorship
