SI Simulation Engineer
Core
Perform pre-layout and post-layout signal integrity simulation for high-speed interfaces to optimize channel structures and ensure performance.
Role type
Senior IC signal integrity simulation engineer
Builds
High-speed networking products (switches, routers, servers, NICs)
Domain
Hardware design / High-speed digital interfaces
Deliverable
production ML models | product features
Required skills
Signal integrity simulation, PCB channel design, Ansys tools (HFSS, SIwave, Q3D, AEDT), high-speed interface standards (DDR4/5, PCIe Gen3-5, 100G-800G Ethernet), channel loss analysis, impedance discontinuity analysis, jitter/eye diagram/BER analysis
Preferred skills
SerDes channel design (25G/56G/112G), switch/router/server/NIC/AI server/backplane product experience, low-loss PCB material knowledge (Dk/Df, copper roughness), IBIS-AMI models, S-parameters, equalization tuning
Technologies
Ansys HFSS, Ansys SIwave, Ansys Q3D, Ansys AEDT, VNA, TDR, oscilloscope, BERT
Responsibilities
Evaluate channel loss, PCB material, stack-up, IC placement, and routing constraints; Build and analyze end-to-end channel models; Optimize high-speed channel structures; Analyze insertion loss, return loss, crosstalk, impedance discontinuity, jitter, eye diagram, and BER performance; Define PCB layout guidelines and routing constraints; Work with EE, layout, mechanical, vendor, and validation teams to resolve SI issues; Support simulation-to-measurement correlation using VNA, TDR, oscilloscope, BERT, or compliance test results
Seniority
Senior, hands-on IC
