Package Health Yield (Senior/Staff/Principal) Engineer, APTD
Core
Develop advanced packaging technology strategies for high-performance memory products (HBM), focusing on test architecture, coverage, yield, and reliability characterization.
Role type
Senior/Staff/Principal IC Package Health Yield Engineer
Builds
High-bandwidth memory (HBM) packages and test vehicles for AI and supercomputing applications
Domain
Semiconductor manufacturing, Advanced Packaging, High-Performance Memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Test architecture definition, Wafer and die-level test coverage optimization, Electrical characterization and failure analysis, DFT co-development, Probe yield debugging, Test flow readiness management, Simulation tools usage, Data analysis and scripting (Python, MATLAB, JMP)
Preferred skills
Experience with complex semiconductor products, Cross-functional collaboration, Problem-solving in high-volume manufacturing environments
Technologies
Python, MATLAB, JMP, Simulation tools, Test equipment
Responsibilities
Define and validate test coverage for wafer and die processes, Perform electrical characterization and failure analysis of advanced packages, Enhance test fail debugging to meet probe yield targets, Contribute to product roadmap from test architecture perspective, Co-work on Test Vehicle (TV) validations, Co-drive customer test flow readiness activities
Seniority
Senior, hands-on IC