Senior Product, Test and Yield Enhancement Engineer - Taiwan
Core
Drive test strategy, failure analysis, and yield enhancement for future generations of the Cerebras Wafer Scale Engine (WSE) in Taiwan.
Role type
Senior IC VLSI product and test engineer
Builds
Wafer-scale AI processors, high-speed I/O, and memory
Domain
Semiconductor manufacturing and AI hardware
Deliverable
production ML models
Required skills
semiconductor test development, silicon debug, test optimization, yield improvement, large parallel processor testing, load board/probe card design, ATE operation, defect characterization, failure isolation
Preferred skills
C/C++/Python/Perl for test-data analysis, OBIRCH/IREM/LADA techniques, high-speed SerDes testing, analog block testing, wafer-scale packaging knowledge
Technologies
Advantest V93000, Teradyne, Tessent, Git
Responsibilities
Develop and optimize production test programs for wafer-scale AI processors; Drive high-volume manufacturing testing with foundries and OSATs; Implement design-for-test strategies (scan, BIST, ATPG); Analyze ATE, Shmoo, and defect data to improve yield; Develop failure-analysis methods for defective cores; Build efficient wafer-level test flows for mesh and NoC architectures; Optimize voltage-frequency limits, power delivery, and thermal behavior; Support wafer and lot disposition decisions.
Seniority
Senior, hands-on IC
