CareerPlan

Principal Design Engineer, DRAM

Boise, Idaho, United States of AmericaFull-time2026-07-17 → 2026-11-10

Core

Define and implement Design-for-Test (DFT) methodology, circuits, and architectures for advanced memory products to ensure testability, robustness, and manufactability.

Role type

Principal Design Engineer (DFT)

Builds

Advanced DRAM memory products

Domain

Semiconductor / Memory / Digital Circuit Design

Required skills

Digital or mixed-signal circuit design, DFT concepts and scan-based methodologies, circuit simulation, cross-functional collaboration

Preferred skills

Complex SOC or memory product design, DFT verification flows and automation, EDA tools, AI-assisted design techniques

Technologies

EDA tools, simulation environments

Responsibilities

Define and implement DFT and testmode requirements for current and future memory products; Design and evaluate new DFT circuit and architectural solutions; Influence early design planning by shaping DFT architecture and reusable design intent; Validate DFT solutions through modeling, simulation, and review; Collaborate across design, verification, product engineering, and manufacturing to meet coverage and quality goals

Seniority

Principal, hands-on IC