MTS, DEG Design Verification
Core
Lead design and verification strategy for advanced DRAM products, driving innovation in verification methodology, coverage closure, and silicon debugging.
Role type
Senior IC design verification engineer (DRAM)
Builds
Advanced memory products (DRAM, DDR5+)
Domain
Semiconductor / Memory / DRAM
Required skills
DRAM verification, circuit analysis at transistor level, simulation tools (HSPICE, Finesim, Verilog, SystemVerilog), CMOS fundamentals, leadership, silicon debugging
Preferred skills
UVM, mixed-signal verification, DDR5+ architectures, verification methodology development, mentoring, Python programming, AI-assisted tools (ClaudeCode)
Technologies
HSPICE, Finesim, Verilog, SystemVerilog, UVM, Python, ClaudeCode
Responsibilities
Lead DRAM design and/or verification innovation, drive technical strategy and execution; Collaborate with global teams to develop and share best-known methods; Drive circuit improvement, verification planning, coverage closure, and silicon debug; Define and implement tools, methodologies, and automation; Provide technical leadership in mixed-signal simulation and signoff strategy; Mentor engineers and serve as a DRAM authority.
Seniority
Senior, hands-on IC with mentorship responsibilities
