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DRAM Architect - Sr Engineer

Boise, Idaho, United States of America💼 Full-time🗓 2026-05-12 → 2026-09-25

Core

Optimize DRAM solutions for power, performance, and cost while pioneering new memory features and system-level innovations.

Role type

Senior IC DRAM Architect

Builds

High-quality, reliable, and power-efficient DRAM solutions

Domain

Semiconductor / Memory and Storage

Deliverable

production ML models | product features

Required skills

DRAM system/component solution design, performance optimization, power efficiency analysis, cost optimization, system behavior analysis, architectural trade-off analysis

Preferred skills

LPDDR5/6, DDR5/6, GDDR6/7 experience, memory system modeling, performance simulation, JEDEC standards familiarity, cross-layer optimization

Technologies

LPDDR5, LPDDR6, DDR5, DDR6, GDDR6, GDDR7, JEDEC standards

Responsibilities

Develop comprehensive DRAM system/component solutions, specifications, and methodologies; Collaborate with multi-functional teams to implement innovative ideas; Analyze system behavior and make data-driven optimizations; Communicate complex technical concepts to engineers

Seniority

Senior, hands-on IC

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