Senior Engineer - Standard Cell Design
Core
Design and maintain standard cells for new DRAM products, developing architectures for emerging technologies and creating automation flows.
Role type
Senior IC standard cell design engineer (DRAM)
Builds
Standard cell libraries and characterization models for DRAM products
Domain
Semiconductor manufacturing / DRAM memory / Analog & Digital IC design
Deliverable
production ML models | product features
Required skills
CMOS circuit design, CMOS device physics, standard cell flow (DTCO to lib release), RTL/GDS flow setup, block level timing analysis, ICC2, Synopsys EDA flow, Finefet, planner, characterization tools (Siliconsmart/Liberate), Cadence Virtuoso, Primetime, Solido Analytics, analog/digital simulation (HSPICE, HSIM, VerilogHDL, FINESIM, Simvision), standard cell layout and verification, scripting (Skill, TCL, Perl, Python)
Preferred skills
DRAM memory experience, analog blocks experience, AI-assisted tools for design and characterization
Technologies
Synopsys EDA, Cadence Virtuoso, ICC2, Primetime, Solido Analytics, HSPICE, HSIM, VerilogHDL, FINESIM, Simvision, Siliconsmart, Liberate, Finefet, planner
Responsibilities
Design and maintain standard cells for new DRAM products; collaborate with DTCO team on stdcells architecture; characterize and model standard cells for timing/power; analyze liberty models for performance, power, and functionality; develop automation test benches and flows; identify design pain points for AI-based automation solutions.
Seniority
Senior, hands-on IC