Advanced Technology Japan Engineer, WoW Bonding
Core
Wafer Bonding Process Engineer responsible for introducing, ramping up, and optimizing next-generation semiconductor packaging technologies.
Role type
Senior IC process engineer (semiconductor packaging)
Builds
Wafer Bonding, Si Grinding, and Bevel Trimming processes for memory and storage solutions
Domain
Semiconductor manufacturing / Packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (manufacturing process optimization)
Required skills
Wafer Bonding, Si Grinding, Bevel Trimming, DOE, SPC, FMEA, English technical communication
Preferred skills
CMP, 3D integration, LabVIEW, FPGA control, Python, MATLAB, project leadership, Japanese communication
Technologies
Wafer Bonding equipment, Si Grinding tools, Bevel Trimming systems, LabVIEW, FPGA, Python, MATLAB
Responsibilities
Develop and optimize Wafer Bonding processes; Integrate Wafer Bonding, Si Grinding, and Bevel Trimming; Evaluate and upgrade equipment; Conduct technical discussions with vendors; Implement SPC metrics and perform abnormality analysis; Reduce risks using FMEA and 8D methodologies; Drive technology development projects for mass production transition; Collaborate with global teams and material suppliers.
