Design Methodology – Principal DRAM Power Integrity Engineer
Core
Develop and standardize EMIR methodology for DRAM products, performing static and dynamic EM/IR and PDN analysis to identify root-cause issues and provide actionable recommendations to design teams.
Role type
Principal DRAM Power Integrity Engineer
Builds
DRAM memory and storage solutions
Domain
Semiconductor / Memory / Power Integrity
Required skills
EMIR analysis, PDN analysis, Ansys RedHawk, Ansys Totem, vectorless IR-drop analysis, root-cause analysis, SoC-level signoff, design flow understanding, automation frameworks
Preferred skills
Python scripting, Tcl scripting, power-modeling, PnR tools, STA tools, SPICE, AI/ML-assisted design flows
Technologies
Ansys RedHawk, Ansys Totem, FusionCompiler, PrimeTime, Make
Responsibilities
Develop and standardize EMIR methodology across DRAM products; Perform static and dynamic EM/IR and PDN analysis using industry-standard tools; Leverage AI-based tools and automation frameworks for PDN analysis; Maintain understanding of the full EMIR flow from netlist to silicon correlation; Partner with cross-functional teams to develop worst-case vectors and standardize analysis; Collaborate with global teams and EDA vendors to improve methodologies; Develop dashboards to track EMIR results and support signoff progression.
Seniority
Principal, hands-on IC
