Member of Technical Staff, SoC Power and Physical Architect, Next-generation HBM Architecture
Core
Drive SoC-level specification for 3D-stacked, high-performance high-bandwidth memory (HBM) products, focusing on power architecture, physical planning, and early SoC design activities.
Role type
Senior IC SoC Power and Physical Architect
Builds
Next-generation HBM memory solutions for emerging AI systems
Domain
Semiconductor / High-Performance Computing / AI Infrastructure
Deliverable
production ML models
Required skills
SoC hardware design, HBM architecture, power delivery networks (PDN), thermal analysis, DFT architecture, floorplanning, EDA toolsets (PrimePower, PrimeShield, RedHawk, ICC2)
Preferred skills
Circuit design, interconnect reasoning, frequency vs. energy tradeoffs
Responsibilities
Define clocking architectures, power sequencing, and on-die signal interfaces; Analyze on-die power delivery networks and full-chip thermal implications; Define DFT architectures and verification requirements; Define SoC floorplans; Compose SoC physical documentation
Seniority
Senior, hands-on IC
