Senior IC PDK Development Engineer
Core
Architect, build, and maintain custom Process Design Kits (PDKs) and physical verification enablements for cryogenic silicon quantum processors.
Role type
Senior IC PDK Development Engineer
Builds
Custom PDK components (Schematic symbols, Layout SKILL PCells, DRC/LVS decks) and Calibre SVRF rule decks for quantum computing chips.
Domain
Semiconductor manufacturing / Quantum computing hardware
Required skills
IC PDK development, Cadence SKILL PCell coding, Cadence Virtuoso customization, Siemens Calibre SVRF rule writing, DRC/LVS error debugging, analog/mixed-signal layout knowledge
Preferred skills
Deep-submicron CMOS node experience (40nm/28nm), MOSFET device modeling integration (BSIM/Verilog-A), cryogenic device enablement
Technologies
Cadence Virtuoso, Cadence SKILL, Siemens Calibre, SVRF
Responsibilities
Develop custom PDK elements from scratch; Create and maintain Calibre SVRF rule decks; Integrate tier-1 foundry PDKs into Cadence Virtuoso; Collaborate with IC designers on physical verification best practices; Document work and evaluate peer layout enablement
Seniority
Senior, hands-on IC
