Principal Validation Lead
Core
Own lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes.
Role type
Principal Validation Lead (Hands-on IC with technical leadership)
Builds
ASIC/SoC silicon bring-up and lab validation platforms
Domain
Semiconductor / High-speed interface validation
Required skills
Silicon bring-up and debug, CXL/PCIe/DDR/HBM/SerDes interface validation, lab equipment operation (oscilloscopes, protocol analyzers, BERTs), lab automation scripting (Python, TCL, shell, MATLAB), cross-functional debug leadership, test planning and methodology, data analysis for high-speed links
Preferred skills
DFT features (scan, BIST, JTAG), signal integrity/power integrity concepts, leading small validation teams, multi-site project experience
Technologies
CXL 3.x, PCIe Gen4/5/6, DDR4/5, HBM2/2E/3, Python, TCL, shell, MATLAB, oscilloscopes, protocol analyzers, logic analyzers, BERTs, pattern generators
Responsibilities
Define validation strategy and test plans, lead silicon bring-up and interface validation, provide technical direction to validation engineers, configure and operate advanced lab equipment, drive lab automation and data analysis infrastructure, analyze large data sets to characterize links, lead root-cause investigations, own validation documentation, mentor junior engineers
Seniority
Principal, hands-on IC with technical leadership
