Digital IC Design Intern, BS - Summer 2027
Core
Intern role focused on digital IC design, RTL development, and verification for high-performance Ethernet PHY chips and SoC subsystems.
Role type
Digital IC Design Intern
Builds
High-performance Ethernet PHY chips, SoC micro-architecture blocks, and accelerators for cloud, AI, storage, and networking.
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features
Required skills
RTL design, static timing analysis, synthesis, power analysis, Verilog, Python, Perl, Tcl, SoC/ASIC design flow
Preferred skills
Experience with Synopsys Primetime, Cadence Virtuoso & Spectre X, Mentor tools
Technologies
Synopsys, Cadence, Mentor
Responsibilities
Develop and verify detailed RTL design blocks, conduct synthesis and timing signoff, debug design issues, investigate new design techniques and flows, collaborate with architecture and physical design teams
Seniority
Intern
