Design Verification- Intern
Core
Intern role focused on developing and verifying next-generation network switch architectures and IPs using System Verilog, UVM, and Python.
Role type
Intern, Design Verification Engineer
Builds
Next-generation network switches and switching product IPs
Domain
Semiconductor, Networking, Digital Logic
Required skills
System Verilog, UVM, Python, C++, Object-Oriented Programming, Digital Logic, Random Verification Techniques, Coverage Analysis, Debugging, Scripting
Responsibilities
Implement new design and verification features, Write verification test plans, Develop complex object-oriented random verification environments, Create and tune tests to achieve coverage goals, Debug simulation failures to root-cause problems, Automate repetitive tasks using scripting languages
