Digital IC Design Engineer, Intern
Core
Design and verify high-speed parallel DSP architectures and PHY designs using CMOS technology for cloud data center and AI networks.
Role type
Digital IC Design Engineer (Intern)
Builds
Next-generation high-speed PAM/Coherent DSPs and PHY designs
Domain
Semiconductor / High-speed DSP / CMOS
Required skills
HDL design, digital verification, DFT design, synthesis, static timing analysis, power analysis, scripting (TCL, Perl, Python, Unix shell), parallel DSP optimization
Preferred skills
Design verification, DFT, digital signal processing
Technologies
CMOS, PAM/Coherent, HDL, TCL, Perl, Python, Unix shell
Responsibilities
Perform digital design tasks using HDL and verification tools, code in scripting languages, optimize and simulate high-speed parallel DSP architectures, analyze parallel DSP optimization challenges, collaborate with cross-functional teams
Seniority
Intern
