Digital IC Design Engineer, Intern
Core
Design and verify high-speed parallel DSP architectures and PHY designs using CMOS technology for cloud data center and AI network infrastructure.
Role type
Digital IC Design Engineer (Intern)
Builds
Next-generation high-speed PAM/Coherent DSPs and PHY designs
Domain
Semiconductor / High-speed Digital Signal Processing
Deliverable
production ML models | product features
Required skills
HDL design, digital verification, DFT design, synthesis, static timing analysis, power analysis, scripting (TCL, Perl, Python, Unix shell), parallel DSP architecture optimization
Preferred skills
Design verification and DFT knowledge, digital signal processing knowledge
Technologies
CMOS technology, PAM/Coherent ecosystem, HDL tools, verification tools
Responsibilities
Perform digital design tasks using HDL and verification tools; Code in scripting languages; Optimize and simulate high-speed parallel DSP architectures; Analyze parallel DSP optimization challenges; Collaborate with cross-functional teams
Seniority
Intern, final-year Master's student or recent graduate
