Design For Test Intern, MS - Summer 2027
Core
Intern role developing DFT architecture, methodology, and IP/chip design for complex SoCs in data center, enterprise, wireless, and automotive markets.
Role type
Intern, Design for Test (DFT) Engineer
Builds
SoC designs for data center, enterprise, wireless, and automotive compute markets
Domain
Semiconductor / Digital Logic / Test Engineering
Required skills
Verilog/System Verilog, DFT concepts, JTAG standards, Boundary Scan, Scan test, Memory BIST/BISR, Functional test, Python, Shell, Tcl
Preferred skills
AI-assisted coding tools, Advanced DFT methodologies
Technologies
Verilog, System Verilog, Python, Shell, Tcl, EDA tools
Responsibilities
Develop block level or chip top DFT and pattern generation flows, Execute DFT insertion and verification flows, Run DFT checks and analyze results, Support DFT flow automation through scripting, Contribute to DFT documentation and methodology improvements, Present intern project results
Seniority
Intern
