Design For Test Intern, MS - Summer 2027
Core
Intern role focused on Design for Test (DFT) architecture, methodology, and verification flows for complex SoC designs in the data center, enterprise, wireless, and automotive markets.
Role type
Intern, Design for Test (DFT) Engineer
Builds
SoC designs for data center, enterprise, wireless, and automotive compute markets
Domain
Semiconductor / SoC Design / DFT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital logic design (Verilog/System Verilog), DFT concepts, JTAG standards, Boundary scan implementation, Scan test, Memory BIST/BISR, Functional test, Scripting (Python, Shell, Tcl)
Preferred skills
AI-assisted coding tools, Advanced DFT methodologies
Technologies
Verilog, System Verilog, Python, Shell, Tcl, Tcl, JTAG
Responsibilities
Develop understanding of block level or chip top DFT and pattern generation flows, Execute DFT insertion and verification flows, Run DFT checks and analyze results, Support DFT flow automation through scripting, Contribute to DFT documentation and methodology improvements, Present intern project results
Seniority
Intern
