Analog Design Engineer
Core
Develop die-to-die chiplet PHY IP solutions for next-generation AI computing platforms.
Role type
Senior Analog/Mixed-Signal Design Engineer
Builds
High-performance chiplet PHY IP (PLLs, SerDes, Tx/Rx blocks) for AI accelerators
Domain
Semiconductor / AI Hardware / High-Speed Interconnects
Deliverable
production ML models | product features | infrastructure
Required skills
Analog/Mixed-Signal IC design in FinFET, PLL/AMS design, high-speed datacomm/SerDes, die-to-die PHY design, silicon bring-up/testing, EDA tools, bias generators, amplifiers, LDOs, ADCs/DACs, oscillators, switched-cap circuits, CTLE, DFE, de-emphasis
Preferred skills
Deep sub-micron technology expertise, cross-functional collaboration, scalable IP methodologies
Technologies
FinFET, EDA tools, SerDes, DDR, PCIe, USB
Responsibilities
Design, verification, layout interaction, tape-out, and silicon bring-up of AMS IP; Collaborate with architecture, digital, verification, and software teams; Optimize analog, digital, and layout for performance, power, and area targets
Seniority
Senior, hands-on IC engineer