Senior Staff- IP RTL Design Engineer
Core
Architect and deliver next-generation UCIe and high-speed mixed signal IP, spanning micro-architecture definition through production-quality RTL.
Role type
Senior Staff IC RTL Design Engineer (High-Speed Interface IP)
Builds
Production-quality RTL for UCIe, HBM, and other high-speed interface IP blocks
Domain
Semiconductor / Digital IC Design / High-Speed Protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog/Verilog, high-speed protocol expertise (UCIe, HBM, Ethernet, DDR, PCIe), RTL sign-off flows (Lint, CDC/RDC), synthesis, STA, SoC architecture
Preferred skills
Low-power design techniques, clocking architectures, post-silicon debug, reusable IP delivery
Technologies
SpyGlass, UCIe, HBM, SystemVerilog, Verilog
Responsibilities
Architect and implement state-of-the-art RTL for high-speed interface IP; Own micro-architecture and RTL development for medium to high-complexity digital blocks; Drive hands-on execution including RTL coding, synthesis, CDC/RDC analysis, linting, debugging, and support for test and bring-up; Partner with Architecture and Verification teams to define test plans and achieve verification closure; Provide technical leadership by mentoring junior engineers and reviewing designs
Seniority
Senior Staff, hands-on IC with technical leadership
