Sr Staff COE Verification Engineer
Core
Design, verify, and deliver IP subsystem building blocks for PCIe/CXL controllers and fabric-level subsystems to power advanced custom chips for hyperscale cloud, AI, and data center customers.
Role type
Sr Staff IC verification engineer (PCIe/CXL protocols)
Builds
Production-ready IP subsystems for PCIe Gen6/Gen7 and CXL 3.0/4.0
Domain
Semiconductor / Custom Compute and Storage / Data Center
Required skills
System Verilog, UVM methodology, PCIe protocol architecture, CXL protocol architecture, ASIC/SoC verification, digital design fundamentals, simulation debugging, coverage-driven verification (CDV)
Preferred skills
System Verilog Assertions (SVA), performance modeling, emulation platforms (Palladium, Veloce), scripting (Python/Perl/Shell), low-power verification (UPF)
Technologies
UVM, System Verilog, PCIe VIP, CXL VIP, Python, Shell, Palladium, Veloce
Responsibilities
Develop and execute verification plans for high-speed memory interfaces; Build and enhance UVM/System Verilog-based verification environments; Perform protocol-level verification for PCIe controllers and PHY interfaces; Debug complex failures using waveforms, logs, and protocol analyzers; Drive functional, code, and assertion coverage closure; Collaborate with design and architecture teams to ensure spec compliance and coverage closure.
Seniority
Sr Staff, hands-on IC with mentorship
