Senior Analog Layout Manager
Core
Lead a team of analog layout designers and perform hands-on macro-level layout work for advanced High-Speed SerDes IPs.
Role type
Senior Analog Layout Manager
Builds
High-Speed SerDes (HSS) IPs for data infrastructure, enterprise, cloud, AI, and carrier architectures
Domain
Semiconductor / Analog Mixed-Signal / High-Speed SerDes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, team leadership, floor planning, LVS/DRC debugging, CALIBRE report interpretation, Synopsys/Cadence tools, Skill/Ample/Perl scripting
Preferred skills
FinFET process technology experience
Technologies
Synopsys, Cadence, CALIBRE, Skill, Ample, Perl
Responsibilities
Hire and lead layout designers, assess schedules and floor plans, perform hands-on macro layout, manage layout schedules, identify and prioritize project risks, synchronize layout schedules with circuit design teams
Seniority
Senior, hands-on IC with management responsibilities