Staff Engineer, Analog Layout
Core
Staff Analog Layout Engineer responsible for developing high-speed connectivity, broadband analog, and computing/storage-memory data-transport products, including high-speed digital blocks, multi-GHz ADC/DAC, PLL/DLL, and clock generation for custom ICs.
Role type
Staff Analog Layout Engineer
Builds
High-performance analog circuits and custom ICs for data infrastructure (enterprise, cloud, AI, carrier architectures)
Domain
Semiconductor / Analog IC Design / High-Speed Connectivity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout methodology, parasitic optimization, advanced process technology (Fin-FET), CALIBRE DRC/ERC/LVS interpretation, Synopsys/Cadence layout tools, project scheduling, cross-functional team leadership
Preferred skills
Scripting (Skill, Ample, Perl), tool testing, flow documentation, technology trend analysis
Technologies
Synopsys, Cadence, CALIBRE, Fin-FET, CMOS
Responsibilities
Own chip/macro layout, manage overall project schedule, lead layout within cross-functional teams, implement project guidelines, contribute to tool testing and script development
Seniority
Staff, hands-on IC with team leadership
