Sr Staff Analog Modeling/Verification Engineer
Core
Creating Verilog/SystemVerilog behavioral models and programming sequences to verify analog circuit behaviors for high-speed optical transceivers.
Role type
Sr Staff Analog Modeling/Verification Engineer
Builds
High-speed and optical transceivers for communication infrastructure
Domain
Semiconductor / Analog Mixed-Signal (AMS) / Optical PHY
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog modeling, CMOS analog circuit design, EDA tool experience (Cadence Virtuoso), AMS simulations, Python scripting
Technologies
Cadence Virtuoso, Python
Responsibilities
Creating Verilog/SystemVerilog behavioral models of analog circuits, Creating programming sequences to verify analog circuit behaviors, Providing support to analog model users for model bring up, AMS simulations to verify leaf cell functionality
Seniority
Sr Staff, hands-on IC