Analog/Mixed-Signal Design Verification Methodology Development Engineer
Core
Establish, streamline, and enhance Analog/Mixed-Signal (AMS) Design Verification (DV) methodologies, coding processes, and integration flows to ensure high-quality pre-silicon verification delivery.
Role type
Senior IC Analog/Mixed-Signal Design Verification Methodology Engineer
Builds
Scalable and portable test benches, test cases, drivers, checkers, assertions, and reference models for AMS IP and chip DV teams.
Domain
Semiconductor / Analog & Mixed-Signal Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification flows, platforms, testbenches)
Required skills
AMS DV flow development, RTL simulation, Gate Level simulation, coverage closure, test bench development, assertion writing, reference model creation, process improvement, cross-team collaboration
Preferred skills
SERDES domain expertise, behavioral modeling, digital verification methodologies
Technologies
RTL, Gate Level simulators, AMS verification tools
Responsibilities
Develop and deploy new AMS DV flows through experiments and demonstrations on real projects (e.g., SERDES), document new processes, support AMS IP/Chip DV teams in establishing DV capabilities, improve AMS DV processes for quality and efficiency, collaborate with global architecture, design, and post-silicon testing teams.
Seniority
Senior, hands-on IC