Technical Lead IC Design/Principal - Micro-architecture, RTL Design
Core
Designing high-speed optical Ethernet transceiver ASICs for cloud computing and data infrastructure, focusing on digital hardware development, verification, and timing closure.
Role type
Senior IC Design/Principal - Micro-architecture, RTL Design
Builds
Optical Ethernet Transceiver ASICs for major cloud computing companies
Domain
Semiconductor / Data Infrastructure / Optical PHY
Deliverable
production ML models | product features
Required skills
Verilog, System Verilog, Python, Unix Shell, RTL implementation, synthesis, static timing analysis, formal equivalence, CDC analysis, functional verification, DSP block modeling, chip bring up, lab validation
Preferred skills
High speed IEEE compliant DSP physical layer products, power and latency optimization, design automation of CAD EDA flow
Technologies
Verilog, System Verilog, Python, Unix Shell, IEEE compliant DSP
Responsibilities
High speed data path RTL implementation, integrate vendor IP, post-silicon debug and correlation, develop ASIC specification and micro-architecture, participate in chip design RTL development and verification, assist in design automation, mentorship of junior team members
Seniority
Senior, hands-on IC