ASIC Design Engineer lll
Core
Design high-performance networking IPs and subsystems for next-generation routers, switches, SmartNICs, DPUs, and AI networking products.
Role type
Senior IC ASIC RTL Design Engineer
Builds
High-speed networking chips (SoCs) for routers, switches, and AI networking hardware
Domain
Networking hardware / Silicon design
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog, Digital logic design, Finite State Machines (FSMs), Clock-domain crossing (CDC), Reset-domain crossing (RDC), Low-power design concepts, AMBA protocols (AXI4, AXI-Stream, APB, AHB), ASIC design flow (Lint, CDC, Synthesis, STA), EDA tools (Synopsys, Cadence, Siemens)
Preferred skills
Networking protocols (Ethernet 10G/25G/100G/400G/800G, TCP/IP, RDMA, PCIe, CXL), Packet-processing pipelines, High-speed SerDes architectures, FPGA prototyping, Performance modeling
Technologies
SystemVerilog, Verilog, Synopsys, Cadence, Siemens, AXI4, AXI-Stream, APB, AHB, Ethernet, TCP/IP, RDMA, PCIe, CXL, SerDes
Responsibilities
Define microarchitecture specifications; Develop RTL for datapath and control-plane logic; Design networking blocks (packet pipelines, DMA, traffic/buffer/queue management, flow control, statistics); Collaborate with architecture, verification, physical design, and firmware teams; Perform linting, CDC analysis, synthesis, and timing closure; Support FPGA prototyping and post-silicon bring-up; Debug functional issues across simulation, emulation, and silicon; Participate in design reviews.
Seniority
Senior, hands-on IC
