Senior Staff Digital Design Engineer
Core
Designing and verifying high-speed optical Ethernet transceiver ASICs for cloud computing infrastructure.
Role type
Senior Staff Digital Design Engineer (ASIC)
Builds
Optical Ethernet Transceiver ASICs for major cloud computing companies
Domain
Semiconductor / Data Infrastructure / Optical Communications
Deliverable
production ML models | product features
Required skills
RTL development (Verilog/System Verilog), static timing analysis, formal equivalence, CDC analysis, gate-level verification, micro-architecture specification, Python, Unix Shell
Preferred skills
Design automation of CAD EDA flow, post-silicon debug and correlation
Technologies
Verilog, System Verilog, Python, Unix Shell, 16nm technology nodes
Responsibilities
Develop high-speed data path and control plane RTL blocks, integrate vendor IP, assist in design automation of CAD EDA flow, perform post-silicon debug and correlation, develop ASIC specification and micro-architecture
Seniority
Senior Staff, hands-on IC design