Staff Digital Verification Engineer
Core
Lead verification efforts for IP, subsystem, and SoC-level projects, developing scalable environments and debugging complex RTL/gate-level issues.
Role type
Staff IC digital verification engineer (ASIC/SoC)
Builds
Reusable verification environments, test cases, scoreboards, monitors, and coverage models for digital chips
Domain
Semiconductor hardware design (ASIC/SoC)
Required skills
System Verilog, UVM, constrained-random testing, coverage-driven verification, gate-level simulation debugging, C/C++ golden model development, fault injection simulation, protocol verification (I2C, AHB/APB, MIPI)
Preferred skills
AI-assisted engineering tools usage, regression infrastructure automation
Technologies
System Verilog, UVM, Xcelium, Questa, C/C++, SVA
Responsibilities
Architect and develop reusable verification environments; Create constrained-random, directed, and scenario-based test cases; Analyze and debug RTL and gate-level simulation failures; Execute and debug fault injection simulations; Collaborate with design, DFT, and physical design teams to resolve issues
Seniority
Staff, hands-on IC
