Senior RISC-V Digital IP Design Engineer
Core
Define and implement configurable RISC-V CPU IP for real embedded products, covering the full lifecycle from architectural exploration to tape-out.
Role type
Senior IC digital design engineer (CPU/RISC-V)
Builds
Reusable processor IP for automotive, industrial, security, and edge-AI applications
Domain
Semiconductor, embedded systems, RISC-V architecture
Deliverable
production ML models | product features
Required skills
CPU/SoC/DSP/accelerator digital IP design, Verilog/SystemVerilog RTL design, processor microarchitecture (pipelines, exceptions, interrupts, memory), design-for-verification, performance/power/area/timing analysis
Preferred skills
RISC-V architecture, custom instruction design, functional safety, security features, compiler interaction, AI acceleration, hardware/software co-design
Technologies
CodAL, UVM, formal verification
Responsibilities
Define RISC-V CPU microarchitecture in CodAL, develop configurable capabilities and custom instructions, translate requirements into design constraints, analyze workloads for performance/efficiency, collaborate with compiler/firmware/verification teams, support safety/security assessments, evaluate AI-assisted design methods
Seniority
Senior, hands-on IC
