Packaging Engineering Intern MS/PhD
Core
Design, development, and analysis of semiconductor packaging technologies (Wirebond, Flip Chip, Modules, SIPs) to enable differentiation for analog and embedded processing products.
Role type
Packaging Engineering Intern (MS/PhD)
Builds
Internal and external solutions for advanced semiconductor packages
Domain
Semiconductor manufacturing and packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor packaging/fabrication knowledge, AutoCAD design, FEM modeling, heat transfer fundamentals, thermodynamics, stress analysis, semiconductor MEMS/3D integration design, CVD/PVD/thin film deposition, electroplating, plasma etch, wafer bumping, optical packaging, plating, adhesion, surface treatment, semiconductor fabrication and characterization tools (VI Scopes, X-ray Inspection, materials characterization, FA techniques)
Preferred skills
ML based package design, optical packaging
Responsibilities
Participate in cross-functional teams to develop packaging solutions, conduct material/mechanical/thermal/electrical characterization, support miniaturization, integration, high reliability, high performance, and low power advancements
Seniority
Intern
