Engineer, APTD CEM – Advanced Packaging Wafer Level Technology Engineering
Core
Develop and optimize wafer-level packaging processes (thinning, backside metal interconnect) to enable next-generation memory and storage solutions.
Role type
Senior IC process development engineer (semiconductor packaging)
Builds
Advanced packaging technologies for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing / Memory and storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Wafer thinning, backside metal interconnect, process parameter setup, equipment evaluation, quality control, data analysis, cross-functional collaboration
Preferred skills
Python, R, SQL, Visual Basic, semiconductor industry experience, leadership
Technologies
Python, R, SQL, Visual Basic
Responsibilities
Establish and improve wafer level process conditions and technologies, upgrade process capabilities to reduce costs, evaluate new equipment and materials, ensure defense coverage through process and testing, conduct continuous data analysis for process controls, integrate manufacturing processes with front-end and assembly teams, provide Process Of Record documentation for production transfer
