Design Verification Engineer
Core
Develop and execute verification strategies to ensure first-pass silicon success for next-generation analog and mixed-signal ICs.
Role type
Design Verification Engineer (Analog/Mixed-Signal)
Builds
Verification plans, test benches, and simulations for analog and mixed-signal ICs
Domain
Semiconductor / Analog Power Products
Required skills
SystemVerilog, UVM, RTL simulation, gate-level simulation, coverage-driven verification, regression automation scripting
Preferred skills
Assertions, timing-aware verification flows, Python/Tcl/Perl scripting
Technologies
Cadence Xcelium, Synopsys VCS
Responsibilities
Develop detailed verification plans; Develop test benches, tests, and simulations at RTL and gate-level; Run coverage regressions to meet defined coverage goals; Track and communicate verification status, issues, and concerns; Work with regression tools and develop scripts to submit cases for regression analysis; Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods, and flows
Seniority
Junior to Mid-level, hands-on IC
