Tapeout Engineer
Core
Converting product and test chip layouts into fracture data, preparing mask orders for shipment, and generating reticle floorplan databases for TI's Advanced Technology Development team.
Role type
Tapeout Engineer (Mask Technology and Pattern Generation)
Builds
Mask data, reticle floorplan databases, and fracture data for product and test chips.
Domain
Semiconductor manufacturing, mask technology, and pattern generation.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Layout conversion, fabrication process basics (FEOL/BEOL), Mask data tools (Cadence Virtuoso, Pegasus, Mentor Calibre), automation development, data integrity management, cross-functional collaboration.
Preferred skills
None stated.
Technologies
Cadence Virtuoso, Pegasus, Mentor Calibre, LAFF, GDS.
Responsibilities
Convert product or technology development test chip layouts into fracture data; prepare mask orders for shipment to vendors; generate reticle floorplan databases; drive automations for the PG/Tapeout process; collaborate with process development, PDK, EDA, and business units; ensure consistent application of methodologies and best practices.
Seniority
Mid-level (2-5 years experience)