Timing closure expert
Core
Design and verify high-speed mixed-signal communication circuits and digital interfaces for leading-edge analog systems.
Role type
Senior IC digital design engineer (timing closure)
Builds
High-performance communication chips
Domain
Semiconductor / High-speed mixed-signal circuits
Deliverable
production ML models | product features
Required skills
RTL coding, simulation, synthesis, timing closure, verification, debugging, test method preparation, data sheet development
Preferred skills
SOC timing closure strategy definition, ECO implementation, PPA trade-off analysis, DFT knowledge, layout awareness, AI/ML flow automation
Technologies
Advanced EDA tools
Responsibilities
Perform RTL coding, simulation, synthesis, timing closure, verification, and debugging of high-speed communication chips; prepare test methods and specifications; assist in application information and data sheet preparation; solve complex design problems; plan and organize independent tasks
Seniority
Senior, hands-on IC