Senior Design Verification Engineer
Core
Ensuring functional correctness and performance of digital modem designs for low-power wireless products across PHY/MAC layers.
Role type
Senior IC design verification engineer (wireless PHY/MAC)
Builds
Robust test environments and verification strategies for digital modem designs
Domain
Semiconductor / Wireless Connectivity (IoT, Smart Home, Smart Cities)
Required skills
SystemVerilog, UVM, digital design fundamentals, debugging simulation results, scripting (Python/Perl), test plan creation, coverage analysis
Preferred skills
Wireless standards (BLE, Wi-Fi, Zigbee), constrained-random verification, SVA, C/C++, MATLAB, mixed-signal verification, low-power methodologies
Technologies
SystemVerilog, UVM, Python, Perl, C, C++, MATLAB
Responsibilities
Define and execute verification strategies for digital modem designs; Develop and maintain scalable verification environments; Create test plans, test benches, and stimuli; Debug and analyze design issues; Track and drive functional and code coverage; Collaborate cross-functionally with firmware and system teams; Support silicon bring-up and correlate pre/post-silicon results
Seniority
Senior, hands-on IC
