Lead Engineer – IC Design (STA Lead )
Core
Lead Physical Design Engineer responsible for end-to-end backend implementation flow, timing sign-off, and PPA optimization for high-performance SoCs and ASICs.
Role type
Senior IC physical design engineer (STA Lead)
Builds
High-performance System-on-Chips (SoCs) and Application-Specific Integrated Circuits (ASICs)
Domain
Semiconductor / VLSI / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: This is a physical design role, but the deliverable category in the prompt options is tricky. The prompt says 'physical/clinical work' for this category. I will map 'physical design of chips' to this category as it is the only one fitting 'physical' work, or strictly follow the list. The list has 'physical/clinical work'. I will use 'physical/clinical work' as the closest match for physical chip design among the provided options, or better yet, re-read the prompt. The prompt says 'Deliverable: <one of: ... | physical/clinical work>'. Chip design is physical work. I will use 'physical/clinical work'.)
Required skills
Static Timing Analysis (STA), Synthesis, Place & Route, Low Power Design (UPF), Physical Verification, EDA Tool Automation, Timing Closure, PPA Optimization
Preferred skills
Hierarchical Design Methodologies, DFT, Floor Planning, Multi-clock/Multi-voltage Designs, Team Leadership (4-10 members), Scripting (Perl/Tcl/Python)
Technologies
Cadence (Genus, Innovus, Tempus, LEC, CLP), Synopsys (ICC2, Fusion Compiler, PrimeTime)
Responsibilities
Manage timing constraints and execute STA for digital blocks and top-level designs; Lead end-to-end physical design flow from RTL handoff to GDSII; Optimize PPA metrics and resolve critical path issues via timing ECOs; Collaborate with front-end RTL, DFT, and verification teams; Mentor junior engineers on design excellence and methodology.
Seniority
Senior, hands-on IC