Senior SI Engineer- Cisco Silicon One
Core
Ensuring performance and reliability of high-speed SerDes IP across silicon, package, and board levels for Cisco's core Switching, Routing, and Wireless products.
Role type
Senior IC signal integrity engineer (high-speed SerDes)
Builds
High-speed SerDes IP for switching, routing, and wireless hardware platforms
Domain
Semiconductor hardware design, high-speed connectivity, AI infrastructure
Required skills
electromagnetic and transmission line theory, 3D/2D EM simulation, SI methodology development, full-system signal integrity analysis, lab correlation, bump-out and ball-out optimization
Preferred skills
HFSS, MATLAB, Python, ADS, HSpice, networking technologies, high-speed connectivity solutions, debugging and validation
Technologies
HFSS, MATLAB, Python, ADS, HSpice
Responsibilities
Provide implementation guidelines and feedback to silicon, package, board, and system design teams; Design and simulate high-speed SerDes signals and perform co-simulation of package and PCB in HFSS; Conduct feasibility studies, design verification, and sign-off processes including lab correlation; Work closely with backend, package, and board design teams for bump-out and ball-out optimization; Drive chip-package-PCB co-design of SerDes at 112Gbps and beyond (via careerplan.io/jobs/2027756-senior-si-engineer-cisco-silicon-one-at-cisco)
Seniority
Senior, hands-on IC
