ASIC DFT DV Technical Leader (Hybrid)
Core
Lead DFT verification planning and test bench development to verify DFT architecture supporting ATE screening, in-system test, and debug needs for Cisco's silicon devices.
Role type
Senior IC ASIC DFT Verification Lead
Builds
Test benches and verification flows for new silicon device models (bare die & stacked die)
Domain
Semiconductor hardware design and verification
Required skills
DFT architecture, test planning, System Verilog, DVE/Verdi debugging, TCL/Python/Perl scripting
Preferred skills
UVM, advanced System Verilog, JTAG protocol, scan architecture, MBIST, boundary scan
Responsibilities
Develop test benches for comprehensive DFT architecture; Collaborate with design and PD teams on test logic integration; Drive reusable test and debug methodologies and standards; Debug complex design issues with minimal mentorship
Seniority
Senior, hands-on IC
