Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)
Core
Develop, document, and implement design rules for ultra-high-speed signaling and analyze substrate signal integrity (SI) and power integrity (PI) for next-generation ASIC packaging.
Role type
Senior IC signal and power integrity hardware ASIC simulation engineer
Builds
High-performance Silicon ASICs for unified routing and switching portfolios (TOR switches to web-scale data centers)
Domain
Semiconductor / High-speed digital design / Advanced packaging
Required skills
High-speed design principles, Transmission Line Theory, electromagnetics, scattering parameters, impedance network analysis, SI/PI simulation, post-layout extraction, SPICE circuit analysis
Preferred skills
High-bandwidth memory (HBM) interface SI, die-to-die interfaces (UCIe), advanced packaging (CoWoS, EMIB, interposer), Vector Network Analysis, IBIS
Technologies
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM flows
Responsibilities
Develop and implement design rules for ultra-high-speed signaling; Analyze substrate SI and PI to collaborate with layout teams; Design and document ASIC packages for high-volume release; Resolve complex technical issues using advanced technology design rules
Seniority
Senior, hands-on IC
